DSPIC30F6013T-20I/PF【PDF 5/228 页】IC DSPIC MCU/DSP 132K 80TQFP

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dsPIC30F6011/6012/6013/6014

DS70117F-page 100

2006 Microchip Technology Inc.

15.12.3

BAUD RATE GENERATOR

In I2C Master mode, the reload value for the BRG is

located in the I2CBRG register. When the BRG is

loaded with this value, the BRG counts down to ‘0’ and

stops until another reload has taken place. If clock arbi-

tration is taking place, for instance, the BRG is reloaded

when the SCL pin is sampled high.

As per the I2C standard, FSCK may be 100 kHz or

400 kHz. However, the user can specify any baud rate

up to 1 MHz. I2CBRG values of ‘0’ or ‘1’ are illegal.

EQUATION 15-1:

SERIAL CLOCK RATE

15.12.4

CLOCK ARBITRATION

Clock arbitration occurs when the master de-asserts

the SCL pin (SCL allowed to float high) during any

receive, transmit, or Restart/Stop condition. When the

SCL pin is allowed to float high, the Baud Rate Gener-

ator is suspended from counting until the SCL pin is

actually sampled high. When the SCL pin is sampled

high, the Baud Rate Generator is reloaded with the

contents of I2CBRG and begins counting. This ensures

that the SCL high time will always be at least one BRG

rollover count in the event that the clock is held low by

an external device.

15.12.5

MULTI-MASTER COMMUNICATION,

BUS COLLISION, AND BUS

ARBITRATION

Multi-master operation support is achieved by bus arbi-

tration. When the master outputs address/data bits

onto the SDA pin, arbitration takes place when the

master outputs a ‘1’ on SDA by letting SDA float high

while another master asserts a ‘0’. When the SCL pin

floats high, data should be stable. If the expected data

on SDA is a ‘1’ and the data sampled on the SDA

pin = 0, then a bus collision has taken place. The

master will set the MI2CIF pulse and reset the master

portion of the I2C port to its Idle state.

If a transmit was in progress when the bus collision

occurred, the transmission is halted, the TBF flag is

cleared, the SDA and SCL lines are de-asserted and a

value can now be written to I2CTRN. When the user

services the I2C master event Interrupt Service Rou-

tine, if the I2C bus is free (i.e., the P bit is set), the user

can resume communication by asserting a Start

condition.

If a Start, Restart, Stop or Acknowledge condition was

in progress when the bus collision occurred, the condi-

tion is aborted, the SDA and SCL lines are de-asserted,

and the respective control bits in the I2CCON register

are cleared to ‘0’. When the user services the bus col-

lision Interrupt Service Routine, and if the I2C bus is

free, the user can resume communication by asserting

a Start condition.

The master will continue to monitor the SDA and SCL

pins, and if a Stop condition occurs, the MI2CIF bit will

be set.

A write to the I2CTRN will start the transmission of data

at the first data bit regardless of where the transmitter

left off when bus collision occurred.

In a multi-master environment, the interrupt generation

on the detection of Start and Stop conditions allows the

determination of when the bus is free. Control of the I2C

bus can be taken when the P bit is set in the I2CSTAT

cleared.

15.13 I2C Module Operation During CPU

Sleep and Idle Modes

15.13.1

I2C OPERATION DURING CPU

SLEEP MODE

When the device enters Sleep mode, all clock sources

to the module are shutdown and stay at logic ‘0’. If

Sleep occurs in the middle of a transmission and the

state machine is partially into a transmission as the

clocks stop, then the transmission is aborted. Similarly,

if Sleep occurs in the middle of a reception, then the

reception is aborted.

15.13.2

I2C OPERATION DURING CPU IDLE

MODE

For the I2C, the I2CSIDL bit selects if the module will

stop on Idle or continue on Idle. If I2CSIDL = 0, the

module will continue operation on assertion of the Idle

mode. If I2CSIDL = 1, the module will stop on Idle.

I2CBRG =

FCY

FSCK

1,111,111

– 1

–

()

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